In MRAM (magnetic random access memory) array cells, information is stored in the free layer of an MTJ (magnetic tunnel junction) or GMR device (giant magneto-resistance). MTJ memory cells are often inserted into the back end of a CMOS process. As shown in FIG. 1, MTJ element 11 is formed on top of patterned bottom conductor lead 12, which is connected to one or more underlying transistors 13 by via 14 (conductive stud). Also seen in FIG. 1 are main silicon body 15, bit line 16, and word line 17.
Currently, bottom conductor lead films include NiCr/Ru100/Ta150/Ru30 (thicknesses in Angstroms), which we use, while other materials, such as Ta, Cr/Ta TaN/Ta have also been reported. In this bottom conductor structure, the Ta (capping) layer, which is formed on top of the Ru conductive layer, is grown as a low resistance (a) phase. It is also noted that treating the low resistance Ta capping layer, prior to depositing the MTJ stack, is necessary for making a high performance MTJ (i.e. high DR/R, V50 (voltage at which dR/R is reduced by 50%) and low switching field Hc).
In the prior art, a TaN/Ta stack has been proposed as a bottom electrode by Parkin in U.S. Pat. No. 6,518,588. This bilayer bottom electrode has some potential issues for MRAM applications. In this patent, one possible bottom electrode structure is for TaN to be the main lateral body of the bottom electrode, which connects to a Cu stud (Ta has the same size as MTJ). TaN has very high resistivity, which in turn affects MRAM electrical performance.
Another possible bottom electrode structure in said patent is for the Ta layer to extend along the TaN layer. In this way, Ta will be the main component of the bottom electrode, providing a lower resistance path. But this Ta layer will be directly exposed to the top ILD (inter-layer dielectric) layer (SiO2, F doped, or C-doped), making it susceptible to oxidation during the ILD process of it does not have a protective layer. This oxidized Ta will have higher resistance, causing bottom electrode performance to deteriorate. Also, it is well known that the interface between Ta and ILD SiO2 is weak, causing significant problems with respect to process integration.
Thus, a major challenge for making a successful MRAM is how to integrate the bottom electrode of the MTJ stack with the standard CMOS back end of line (BEOL) process. To get better electrical performance, the bottom electrode must show low sheet resistance and low contact resistance with the underlying studs that connect the MTJ to the transistors.
To get lower resistance for the bottom electrode, the Ta film needs to be in the alpha crystalline phase. It has been shown that alpha Ta is obtained if deposited on a TaN layer (>10 Å). As already noted, bilayer TaN/Ta as a bottom electrode is associated with some potential problems such as high resistance, easy oxidation, and poor adhesion to ILD layers. The present invention discloses a structure/method that overcomes these problems without sacrificing the advantages.
A routine search of the prior art was performed with the following references of interest being found:
In U.S. Pat. No. 6,518,588, Parkin et al. describe a TaN/Ta lead. U.S. Pat. No. 6,703,654 (Horng et al), assigned to a common assignee with the present invention, discloses a NiCr seed layer for the bottom electrode. U.S. Pat. 6,841,484 (Ping et al) discloses a Ta or TaN bottom electrode and, in U.S. Pat. 6,713,801, Sin et al. describe an alpha-Ta lead.
U.S. Pat. Nos. 6,912,107 and 6,835,423 (Chen et al.) describe a TaN diffusion barrier layer on a metal lead. U.S. Pat. No. 6,803,615 (Sin et al.) teaches that an AFM layer and an AFM seed layer may be formed over the bottom lead which may be W, Cu, or Al.